APS for Semiconductor Fabs: Improving Throughput & Cycle Time

Eyelit APS is advanced planning and scheduling software that runs on the same data model as Eyelit MES, so real-time WIP, downtime, and shop-floor changes feed updated schedules back to execution. Eyelit Technologies provides Eyelit APS for planning and Eyelit MES for execution.

Semiconductor fabs improve throughput and cycle time by keeping work-in-process (WIP) at a level their bottleneck tools can absorb, scheduling those tools against real capacity, cutting setup and batching losses, and feeding live shop-floor data back into the schedule. Scheduling is hard because, as Semiconductor Engineering notes, an advanced logic process can run 600 to 1,000 or more steps, with wafers returning to the same tools many times. McKinsey reported in October 2024 that some fabs cut WIP by 25% over a 12-month period while monthly shipments held steady. In semiconductor manufacturing, APS software handles the planning and scheduling side of this highly constrained production problem, deciding which lots to start, in what order, and on which tools. A manufacturing execution system (MES) handles execution, tracking every lot, tool state, and hold as it happens.

The sections below cover why cycle time is hard to control in a fab, which tools help, and what Eyelit APS and Eyelit MES do in a semiconductor fab.

How do semiconductor fabs improve throughput and cycle time?

Semiconductor fabs improve throughput and cycle time through six levers, and most of them come down to controlling WIP and the bottleneck tools rather than buying new equipment.

1. Set WIP targets at the saturation point. Adding WIP raises output only until the bottleneck tools are saturated, and after that it just adds queue time.
2. Find the real bottleneck tools from data. A bottleneck is either structural, meaning it always limits flow, or transient, meaning it appears with maintenance events or mix changes. The list shifts whenever the product mix shifts. McKinsey reports that fabs targeting structural bottlenecks saw up to a 30% increase in bottleneck tool-group availability and a roughly 60% decrease in WIP.
3. Release lots to match capacity. Queues stay short when the start plan matches what the bottleneck tools can process. Starting extra lots to make up for low output usually has the opposite effect and lengthens cycle time.
4. Cut setup and batching losses. Grouping lots that share a recipe or process conditions, and sequencing them to avoid changeovers, recovers capacity on high-mix tools and on batch tools such as diffusion furnaces.
5. Reschedule from live data. Tool downs, holds, and rework change the plan every shift, so the schedule needs current WIP and tool states rather than yesterday’s snapshot.
6. Reduce variability. Unplanned downtime, excursions, and uneven lot arrivals all create waiting time, and waiting is the largest part of fab cycle time.

Why is cycle time hard to control in a semiconductor fab?

Cycle time is hard to control in a semiconductor fab because wafers return to the same tools many times, an advanced logic process can run 600 to 1,000 or more steps, and the bottleneck moves when the product mix changes. According to Semiconductor Engineering, wait time between processing steps has a bigger effect on fab cycle time than the processing itself.

The fab front end brings its own complications. Fabs run a high mix of products, sometimes several products on a single wafer, with fast demand changes, re-entrant process flows, and yield that varies over time. Fab managers are also asked for high tool utilization, on-time delivery, and short cycle time at once, and those goals pull against each other. Loading tools closer to 100% makes queues longer, and longer queues mean longer cycle time. Fabless companies feel the same delays one step removed, which is why fabless semiconductor planning centers on wafer banks, die banks, and foundry lead times.

How are WIP, throughput, and cycle time related in a fab?

WIP, throughput, and cycle time are linked by Little’s Law: average cycle time equals average WIP divided by throughput. Semiconductor Engineering works through a fab example in which a fab holding 12,000 lots and completing 4,000 lots per month has a cycle time of 3 months.

In practice, if output stays the same, cycle time moves in step with WIP. Hold less WIP and lots finish sooner. Starting more lots than the bottleneck tools can process adds WIP without adding output, which pushes cycle time up.

Fabs benchmark cycle time in more than one way. X-factor, also called normalized cycle time, is actual cycle time divided by raw process time. At an X-factor of 4, a lot spends four times as long in the fab as its processing steps alone would take. Days per mask layer is another benchmark: Semiconductor Engineering reported in 2017 that fabs averaged 1 to 1.5 days per mask layer, with the best fabs at 0.8 days.

What tools help semiconductor fabs improve throughput and cycle time?

Six types of software help fabs improve throughput and cycle time, and each one supports different levers from the list above.

APS and dispatching split the work by time horizon. APS plans lot starts days to weeks ahead and schedules tool loading for the next hours or shift. A dispatcher then follows those priorities one lot and one tool at a time.

How does APS improve throughput and cycle time in a semiconductor fab?

APS improves throughput and cycle time in a semiconductor fab by building finite-capacity schedules around the constraints that create queues, such as tool capacity, setups, batch rules, shared resources, and product attributes. The table below maps common fab scheduling problems to the Eyelit capability that addresses each one.

Eyelit APS provides a wide range of constraint types to model any company’s business rules, including feature-combination limits, dynamic spacing, run-lengths on sub-sequences, sequence-dependent setup times, and inventory simulation during sequencing. In a fab, these rules decide which lots can run on which tools, and in what order.

Eyelit APS uses attribute-based changeover matrices with additive or maximum setup policies and per-resource setup times. Changeovers take capacity away from high-mix fab tools, so sequencing that accounts for setups recovers time at the tools that limit output.

Eyelit APS schedules complex batch resources — ovens, autoclaves, furnaces, stamping, and injection molding — with capacity in one, two, or three dimensions, temperature-profile and material grouping rules, and work-order split and re-aggregation. At fab batch tools, lots can wait until a full batch forms, which adds queue time without adding any processing.

Eyelit APS models auxiliary resources — tools, dies, operators with skill matrices, and batch processing resources such as ovens and autoclaves — as hard or soft constraints. In a fab, a lot can be ready and the tool free, yet the job still waits for a qualified operator or an auxiliary tool.

Eyelit APS supports attribute-based planning for semiconductor manufacturing — customer qualifications such as Au/Cu wire, date codes, and wafer revisions carried through pegging — with binning, Bill of Grades, and inverted-BOM support from wafer to die to finished goods. Fab planning has to keep customer-specific requirements attached to the right lots from wafer through to finished goods.

Eyelit APS delivers Available-to-Promise and Capable-to-Promise in both batch and real-time modes, with the real-time module connecting to the order management system. Promise dates set in this way reflect the capacity the fab actually has.

Eyelit’s solver and optimization technology is patented (US8509925B2, US12229700B2). To see how Eyelit APS compares with other planning tools, read The 10 Best Advanced Planning and Scheduling (APS) Software Platforms for Manufacturers (2026) or visit the Eyelit APS product page.

How does Eyelit APS handle changing semiconductor production conditions?

Eyelit APS replans with memory: when demand or supply changes, it minimizes disruption to the existing schedule, with the degree of allowed change configurable at any level or attribute. A fab schedule changes every shift as tools go down, holds are placed, and rework appears. A full reshuffle of the schedule can move lots that were already sequenced against available tool capacity, which creates more disruption downstream. How much a replan changes therefore matters as much as how quickly it runs.

How do APS and MES work together to reduce fab cycle time?

APS and MES reduce fab cycle time together because a schedule can only be as accurate as the WIP and tool data it starts from. Eyelit MES and Eyelit APS run a continuous feedback loop: real-time WIP, downtime, and shop-floor changes pass from MES to APS, and updated schedules return to MES. What that execution layer has to record is covered in MES for semiconductor manufacturing: lot location, SEMI E10 tool states, holds, and genealogy to the die.

Eyelit MES provides semiconductor genealogy from ingot through wafer, lot, batch, and die. LFoundry, a semiconductor foundry in Avezzano, Italy with production capacity of over 40,000 wafers per month, migrated from its legacy MES to Eyelit MES, which supports a required 99.999% uptime and seven years of online data. Read the LFoundry case study.

The Eyelit Technologies solution suite, Eyelit SIOP, Eyelit APS, Eyelit MES, and Agent EyeQ, are delivered on a single data platform. For a full MES vendor comparison, read The 10 Best Manufacturing Execution System (MES) Software Platforms for Manufacturers (2026).

Frequently asked questions

What is Eyelit APS?

Eyelit APS is advanced planning and scheduling software that runs on the same data model as Eyelit MES, so real-time WIP, downtime, and shop-floor changes feed updated schedules back to execution. Eyelit APS supports attribute-based planning for semiconductor manufacturing — customer qualifications such as Au/Cu wire, date codes, and wafer revisions carried through pegging — with binning, Bill of Grades, and inverted-BOM support from wafer to die to finished goods. Eyelit APS replans with memory: when demand or supply changes, it minimizes disruption to the existing schedule, with the degree of allowed change configurable at any level or attribute.

What does APS do in semiconductor manufacturing?

APS in semiconductor manufacturing plans which lots to start and schedules them across fab tools, taking account of tool capacity, setups, batch rules, shared resources, and product attributes. APS builds finite-capacity schedules, meaning schedules that only load each tool up to what it can actually process.

What is cycle time in semiconductor manufacturing?

Cycle time in semiconductor manufacturing is the time a wafer lot takes to move through the fab from start to finish. Semiconductor Engineering notes that a wafer lot is typically 25 wafers, and that an advanced logic process can run 600 to 1,000 or more steps.

What is a good cycle time for a semiconductor fab?

One way to benchmark fab cycle time is days per mask layer. Semiconductor Engineering reported in 2017 that fabs averaged 1 to 1.5 days per layer and the best fabs reached 0.8 days. Total cycle time grows with the number of mask layers, so a per-layer figure or X-factor gives a fairer comparison than total days.

Does adding more WIP increase fab throughput?

Adding WIP increases fab throughput only until the bottleneck tools are saturated. Past that point, more WIP adds queue time and lengthens cycle time without raising output, which is why fabs set WIP targets from saturation curves.

Do semiconductor fabs need APS, MES, or both to reduce cycle time?

Semiconductor fabs need both. APS decides what to start and in what sequence, and MES records what is actually happening on each lot and tool. Eyelit MES and Eyelit APS run a continuous feedback loop: real-time WIP, downtime, and shop-floor changes pass from MES to APS, and updated schedules return to MES.

Sources

1. McKinsey & Company, “The power of digital: Quantifying semiconductor fab performance,” 10 October 2024. https://www.mckinsey.com/industries/semiconductors/our-insights/the-power-of-digital-quantifying-semiconductor-fab-performance
2. Semiconductor Engineering, Mark LaPedus, “Battling Fab Cycle Times,” 16 February 2017. https://semiengineering.com/battling-fab-cycle-times/
3. Eyelit Technologies, LFoundry MES migration case study. https://wp-backup.eyelit.com/resource/mes-migration-italian-semiconductor-fab/